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Addressing Memory Exploits to Enable Digital Security by Design

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Manage episode 382903232 series 3527547
Content provided by AspenCore. All podcast content including episodes, graphics, and podcast descriptions are uploaded and provided directly by AspenCore or their podcast platform partner. If you believe someone is using your copyrighted work without your permission, you can follow the process outlined here https://player.fm/legal.

In this episode of the Embedded Edge podcast, we talk to industry veteran John Goodacre about an initiative he is leading to make computer systems architecture more ‘secure by design’ by addressing memory safety exploits. This involves use of the CHERI-enabled RISC processors that are gaining significant academic and industrial interest.

  continue reading

38 episodes

Artwork
iconShare
 
Manage episode 382903232 series 3527547
Content provided by AspenCore. All podcast content including episodes, graphics, and podcast descriptions are uploaded and provided directly by AspenCore or their podcast platform partner. If you believe someone is using your copyrighted work without your permission, you can follow the process outlined here https://player.fm/legal.

In this episode of the Embedded Edge podcast, we talk to industry veteran John Goodacre about an initiative he is leading to make computer systems architecture more ‘secure by design’ by addressing memory safety exploits. This involves use of the CHERI-enabled RISC processors that are gaining significant academic and industrial interest.

  continue reading

38 episodes

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